1. Field of the Invention
The present invention generally relates to logic circuits for code conversion and electronic integrated circuits comprising or including such circuits and, more particularly, to the design and architecture of such circuits which can perform code conversion with increased speed particularly for address decoding.
2. Description of the Prior Art
Since the early development of integrated circuits, it has been possible to place more devices on a single chip or in a single circuit package than can be individually accessed with a convenient number of connections to the chip or package. While there is no theoretical limit on the number of connections which can be made to a chip or circuit package, as a practical matter only the most complex of integrated circuits are provided with external connections which number more than a few hundred. As an extreme example, memories which provide even a modest number of individually accessible storage devices, by current standards, are of a size which does not permit external connections to individual cells (e.g. two to four flip-flops or logic circuits in a so-called dual in-line pin (DIP) package is exemplary of a commercial limit on individual accessibility which has been generally observed).
For this reason, it has been customary for many years to provide a decoder on chips which include more than a very few individually accessible devices of a similar type. By this rather simple and straight-forward expedient, upwards of several million memory cells which may be placed on a single chip in accordance with current dynamic memory technology may be accessed with only approximately twenty bits of address code; a logic circuit decoder placed on a small portion of the chip in a compact layout providing selection of a particular bit or device (usually as the intersection of a word line and a bit line by separately decoding low- and high-order bits of the address as row and column addresses) providing a code conversion for selection. Similarly, it may be convenient for various design reasons, such as refresh of dynamic circuits, to partition the device into sections or sub-systems where individual bit access is enabled by simple decoding of one or very few address bits for individual partition enablement while allowing some operations to be carried out in all or a plurality of partitions. Other types of code conversion are well-known for decoding purposes in integrated circuit structure for accommodation of numerous other or specialized functions.
In digital logic circuits and circuits for data processing applications, in general, greatest generality (and, hence, greatest operational flexibility) is achieved when a selection function results from a code conversion- More specifically, many code conversion applications involve a conversion from an arbitrary binary code (e.g. hex, excess-3, etc.) into a one-of-n code in which a unique signal (hence "selection") will appear on a single one of a plurality of output lines. Such a unique selection signal allows direct enablement of circuits or devices with simplified interconnection wiring as well as a reduction in the component count and layout complexity of the circuits since the detection of conditions when enablement should occur (or at least a portion thereof) is transferred to the code converter.
In order to obtain greater switching speed from logic circuits in general, there has been much recent interest in so-called dynamic logic circuits, sometimes referred to more simply as "dynamic circuits" or "dynamic logic". (All of these terms should be understood to be distinct from the term "dynamic memory", mentioned above, which requires refresh (generally of capacitive storage elements which are subject to leakage) and may include a large number of static logic circuits as well as dynamic logic circuits, as particular designs and requirements of performance and function may dictate.)
The basic principle of dynamic logic circuits is to exploit the inherent asymmetries in response characteristics by precharging the logic circuit and individual devices therein to a logic state from which it may be most rapidly switched to the opposite logic state and then only if necessitated by the inputs applied thereto when "evaluation" of the inputs is performed at the termination of or subsequent to precharge (e.g. after "reset" if a reset operation is provided). Such a mode of operation also inherently provides latching and substantial noise immunity as well as allowing the size of many transistors in the circuit to be reduced in comparison with the necessary size of the transistors which would be required to obtain a more symmetrical response or static operation.
Timing of signals, however, is relatively critical in dynamic logic circuits and inputs must be present at inputs prior to evaluation. For this reason, it is common practice to separately "receive" and latch input signals prior to evaluation by dynamic logic; requiring separately clocked "evaluation" of the input signal in order to latch the input onto the dynamic logic prior to evaluation. Error recovery generally cannot be accomplished in the same operational cycle due to the inherent latching until subsequent reset and/or precharge are performed. Further, each stage of the propagation of signals through dynamic logic circuits, particularly if serially connected, must be conducted in a sequence. Therefore, there is a theoretical time penalty for each serial stage of dynamic logic. Highest propagation speed through a plurality of dynamic logic stages may require relatively complex sequencing logic for reset and precharge signals. So-called self-resetting dynamic logic develops a sequence of reset and/or precharge signals by detection of the arrival of a stable logic signal at an output of the circuit; thus requiring additional logic stages and further complicating the sequence of reset and precharge signals which are required for correct operation.
Additionally, while decoder circuit complexity is generally a function of the number of address signal combinations which must be decoded, the architecture of such decoders is generally a matter of the technology with which the logic function is implemented. Therefore, for a given technology, such as dynamic logic circuits, there has been a degree of circuit complexity which could not be reduced and which has limited performance regardless of the simplicity of the code conversion function which was required (e.g. one of two, one of four, two of four, etc. as contrasted, for example, with word line or bit line decoders which might be encountered in large memory addressing schemes). While such complexity of architecture might be tolerable in large decoders, the operational overhead in complex sequencing of operations is disproportionately expensive to fabricate and compromising to operational speed of decoders of more simple function.